Instruction pipelines having a plurality of instruction fetching and processing stages or phases, cannot be gracefully interrupted for certain sequential patterns of instructions in the pipeline. Attempts have been made in the prior art to address this problem, for example U.S. Pat. No. 3,793,631 describes a modified pipeline processor which allows concurrent instruction execution and next instruction fetch operations. An interrupt mechanism described in the patent is of a conventional design so that when an interrupt is accepted, it allows the current operation to complete itself and then branches to the interrupt routine. This imposes the disadvantage that all interrupts must wait until the longest operation is completed before the interrupt can be executed.
Another instruction pipelined processor is described in the copending M. R. Cosgrove, et al. patent application entitled "Instruction Address Stack in the Data Memory of an Instruction-Pipelined Processor, Ser. No. 280,417, filed June 30, 1981 (assigned to the common assignee), now U.S. Pat. No. 4,399,507.
The interrupt processor invention disclosed herein finds application in conjunction with the instruction pipeline of Cosgrove, et al. Thus, the following description of the Cosgrove, et al. instruction pipeline is provided as a background to the interrupt processor invention herein. The four instruction pipeline stages or phases shown in FIG. 1 of Cosgrove, et al. are:
1. I Fetch and Sequence Control, which performs program sequencing, branching, and instruction fetching. PA1 2. Address Generator, which contains base and index registers and generates data storage addresses. PA1 3. Data Storage Controller, which controls reads and writes of the data store. PA1 4. Arithmetic/Logic Unit (ALU), which performs arithmetic operations and contains data registers. PA1 a. interrupting a sequence of instructions which execute out-of-order in a pipelined machine, and PA1 b. allowing a subsequent return to the interrupted program to resume processing of that program without error.
Each machine instruction passes through these four stages, one stage at a time, each cycle. Being pipelined, a new instruction enters the pipe in the first stage each cycle. Thus, there may be four instructions in different stages of execution in the pipeline at any one time. Different types of instructions are executed in different stages of the pipeline. An unconditional branch, for example, is executed in the first stage in its first cycle of the pipeline. An add operation, on the other hand, does not get to the ALU stage to complete its execution until the fourth cycle of its staging through the pipeline. These different cycles of instruction execution for different classes of instructions can cause out-of-order execution of the programmed instructions. For most efficient utilization of the machine, the programmer (with the aid of an optimizing assembler) should actually take advantage of out-of-order execution to keep the pipeline fully running with a new instruction each cycle. By taking advantage of the out-of-order execution, the optimized code will be incompatible with running on a machine that would fully execute each instruction, one instruction at a time. It is also incompatible with running on this machine and being arbitrarily interrupted at the completion of any instruction.
To characterize the pipelined execution in the Cosgrove, et al. processor, consider the following sequence of operations which would be used in an eight way branch based on three compare operations: